The present invention relates to a data transfer control circuit and, more particularly, a data transfer circuit with can achieve DMA (direct memory access).
An intelligent disk memory system has a CPU, a DMA, a disk access device and a cache memory which are used to sequentially write pieces of data in a disk memory or sequentially read them from the disk memory. The cache memory has memory locations corresponding to one track of the disk memory. The CPU designates a part of the cache memory as a transfer area. The initial and end addresses of the transfer area are set in the DMA. The DMA controls the data transfer between the cache memory and the disk access device. The CPU instructs the disk access device to make an access to that part of the disk memory which corresponds to the transfer area. Once the disk access device has accessed said part of the disk, it drives a read/write head to write data in, or read data from the disk memory. The CPU may control the data transfer between the cache memory and an external computer. This control can be performed at any time, except when the DMA is operating.
The known DMA has two registers. The first register stores the initial address of the transfer area, and the second register stores the end address of the area. The data in the first register is supplied to the cache memory as a transfer address. It is incremented until it becomes equal to the data stored in the second register. When the transfer data are supplied to the cache memory, all memory locations of the transfer area are designated in preparation of the data transfer. For example, when the initial address data specifies one of the memory locations in order to write data from this location to the disk memory, the data is supplied to the disk access device. The read/write head is driven, thus writing the data in said portion of the disk memory. Upon completion of the data transfer, the data in the first register of the DMA is incremented.
With the disk memory system, however, the data transfer between the disk and cache memory cannot often be started immediately after the disk access device has received an access instruction from the CPU. This is because the disk access device must wait until the head reaches a specified part of the rotating disk memory (i.e., the portion corresponding to the initial address of the transfer area). When the disk memory is a floppy disk, it needs about 167 ms to rotate once. This time is extremely long in terms of the operation speeds of the CPU, DMA and cache memory. While the DMA is not operating, the CPU can process a considerably large amount of data.
The setup time, which lapses after the disk access device has received an access instruction until the data writing or reading of the disk starts, is determined by the distance between the read/write head and the specified part of the disk. When this distance is long, the setup time is proportionally long, and the data is inevitably transferred at low speed between the cache memory and the disk memory.